1. Field of the Invention
The invention relates to memory controllers, and more particularly to ping-pong buffers of memory controllers.
2. Description of the Related Art
A memory is used by a host for data storage. For example, a flash memory comprises a plurality of blocks, each block comprises a plurality of pages, and each page can store a plurality of data sectors. The host does not directly access data from memory. When the host wants to read data stored in the memory, the host sends a read command to a controller, and the controller then reads data from the memory according to the read command, and then delivers the data to the host. When the host wants to write data to the memory, the host sends data and a write command to the controller, and the controller then writes the data to the memory according to the write command.
When the controller reads data from the memory, the controller sends information about an address range determined by the host to the memory, and the memory then outputs data stored in the address range to the controller. The controller comprises a ping-pong buffer which further comprises at least two buffers. When the controller receives data output by the memory, the controller stores the received data in a buffer of the ping-pong buffer, and the host then reads data from the buffer.
When the address range read by the host comprises a plurality of pages, the memory sequentially reads the pages and then outputs data stored in the pages to the controller. Each page of the memory stores a plurality of data sectors. When a target read page is read, the memory sequentially reads data sectors stored in the target read page, and then sequentially outputs the data sectors to the controller. When all data sectors of a current page have been output by the memory, the memory must switch a target read page from the current page to a next page. Switching of a target read page requires a predetermined time period. Referring to FIG. 1, a schematic diagram of timings of read operations of a memory is shown. First, the memory spends a time period T1 to switch a target read page to a first page of the memory. Assume that the first page stores K data sectors. The memory then spends K time periods T2 to respectively read a first sector, a second sector, . . . , and a K-th sector of the first page and respectively output the first sector, the second sector, . . . , and the K-th sector of the first page to a ping-pong buffer of the controller. The memory then spends another time period T1 to switch the target read page from the first page to a second page of the memory. The memory then spends K time periods T2 to respectively read a first sector, a second sector, . . . , and a K-th sector of the second page and respectively output the first sector, the second sector, . . . , and the K-th sector of the second page to a ping-pong buffer of the controller.
Because changing of a target read page requires an extra time period T1, when a memory changes the target read page, the ping-pong buffer of the controller must wait for a longer period (T1+T2) to receive a next data sector, and the host also must wait a longer period to access data from the ping-pong buffer of the controller. Because an address range read by the host usually comprises a plurality of pages, when data stored in the address range is read, the memory must frequently switch a target read page, causing a long delay when executing the read operation; thus, degrading system performance. Thus, a method for handling data read out from a memory is required to shorten a delay period of a read operation; thereby improving system performance.